/* ==============================================================================
Project Name	: 6-Axis controller for robotic arm with 3 phase motor

Model Number	: FD0B098

File Name		: Fpga.h

Description		: Header file of fpga.c.

=================================================================================
 History:

 Date			Version			Remarks
---------------------------------------------------------------------------------

============================================================================== */
#ifndef _FPGA_H_
#define _FPGA_H_

/*** INCLUDES ******************************************************************/
#ifdef MATLAB_MEX_FILE
#include "tmwtypes.h"
#define DELAY_US(A) {}
#else
#include "F2837xD_device.h"     // F2837xD Headerfile Include File
#include "F2837xD_Examples.h"   // F2837xD Examples Include File
#include "rtwtypes.h"
#include "F28x_Project.h"
#endif

typedef unsigned int    	Uint16;
typedef unsigned long   	Uint32;


#define	ENC_CTRL	0
#define	ENC_STATUS	1
#define IO_INPUT 8
#define IO_OUTPUT 9

#define PWM_MOTOR1_PERIOD 16
#define PWM_MOTOR1_U_DUTY 17
#define PWM_MOTOR1_V_DUTY 18
#define PWM_MOTOR1_W_DUTY 19
#define	ENC_RDG_MOTOR1	24
#define ENC_ERR_MOTOR1 25
#define EEPROM_ACC_WR_MOTOR1 26
#define EEPROM_ACC_RD_MOTOR1 27

#define PWM_MOTOR2_PERIOD 32
#define PWM_MOTOR2_U_DUTY 33
#define PWM_MOTOR2_V_DUTY 34
#define PWM_MOTOR2_W_DUTY 35
#define	ENC_RDG_MOTOR2	40
#define ENC_ERR_MOTOR2 41
#define EEPROM_ACC_WR_MOTOR2 42
#define EEPROM_ACC_RD_MOTOR2 43

#define PWM_MOTOR3_PERIOD 48
#define PWM_MOTOR3_U_DUTY 49
#define PWM_MOTOR3_V_DUTY 50
#define PWM_MOTOR3_W_DUTY 51
#define	ENC_RDG_MOTOR3	56
#define ENC_ERR_MOTOR3 57
#define EEPROM_ACC_WR_MOTOR3 58
#define EEPROM_ACC_RD_MOTOR3 59

#define PWM_MOTOR4_PERIOD 64
#define PWM_MOTOR4_U_DUTY 65
#define PWM_MOTOR4_V_DUTY 66
#define PWM_MOTOR4_W_DUTY 67
#define	ENC_RDG_MOTOR4	72
#define ENC_ERR_MOTOR4 73
#define EEPROM_ACC_WR_MOTOR4 74
#define EEPROM_ACC_RD_MOTOR4 75

#define PWM_MOTOR5_PERIOD 80
#define PWM_MOTOR5_U_DUTY 81
#define PWM_MOTOR5_V_DUTY 82
#define PWM_MOTOR5_W_DUTY 83
#define	ENC_RDG_MOTOR5	88
#define ENC_ERR_MOTOR5 89
#define EEPROM_ACC_WR_MOTOR5 90
#define EEPROM_ACC_RD_MOTOR5 91

#define PWM_MOTOR6_PERIOD 96
#define PWM_MOTOR6_U_DUTY 97
#define PWM_MOTOR6_V_DUTY 98
#define PWM_MOTOR6_W_DUTY 99
#define	ENC_RDG_MOTOR6	104
#define ENC_ERR_MOTOR6 105
#define EEPROM_ACC_WR_MOTOR6 106
#define EEPROM_ACC_RD_MOTOR6 107


/*** DEFINES *******************************************************************/
#define	ENC1_ENABLE_READ_POSITION		0x00000001
#define	ENC1_ACCESS_EEPROM				0x00000002
#define	ENC1_RESET_ERROR				0x00000004
#define ENC1_RESET_ST_POSITION			0x00000008
#define	ENC1_RESET_MT_POSITION			0x00000010

#define	ENC2_ENABLE_READ_POSITION		0x00000020	
#define	ENC2_ACCESS_EEPROM				0x00000040
#define	ENC2_RESET_ERROR				0x00000080
#define ENC2_RESET_ST_POSITION			0x00000100
#define	ENC2_RESET_MT_POSITION			0x00000200

#define	ENC3_ENABLE_READ_POSITION		0x00000400
#define	ENC3_ACCESS_EEPROM				0x00000800
#define	ENC3_RESET_ERROR				0x00001000
#define ENC3_RESET_ST_POSITION			0x00002000
#define	ENC3_RESET_MT_POSITION			0x00004000

#define	ENC4_ENABLE_READ_POSITION		0x00008000
#define	ENC4_ACCESS_EEPROM				0x00010000
#define	ENC4_RESET_ERROR				0x00020000
#define ENC4_RESET_ST_POSITION			0x00040000
#define	ENC4_RESET_MT_POSITION			0x00080000

#define	ENC5_ENABLE_READ_POSITION		0x00100000
#define	ENC5_ACCESS_EEPROM				0x00200000
#define	ENC5_RESET_ERROR				0x00400000
#define ENC5_RESET_ST_POSITION			0x00800000
#define	ENC5_RESET_MT_POSITION			0x01000000

#define	ENC6_ENABLE_READ_POSITION		0x02000000
#define	ENC6_ACCESS_EEPROM				0x04000000
#define	ENC6_RESET_ERROR				0x08000000
#define ENC6_RESET_ST_POSITION			0x10000000
#define	ENC6_RESET_MT_POSITION			0x20000000

#define FPGA_SetupEnablePin()			FPGA_SetupEnablePin_func()
#define FPGA_Enable()					FPGA_Enable_func();
#define FPGA_Disable()					FPGA_Disable_func();


void FPGA_SetupEnablePin_func(void);
void FPGA_Enable_func(void);
void FPGA_Disable_func(void);

/*** STRUCTS & UNIONS **********************************************************/
union FPGA_CONTROL_REG
{
	Uint32	all;
	struct
	{
		Uint32  Enc1_EnableReadPosition:1;
		Uint32	Enc1_AccessEeprom:1;
		Uint32  Enc1_ResetErrors:1;
		Uint32	Enc1_ResetSTPosition:1;
		Uint32	Enc1_ResetMTPosition:1;
		Uint32  Enc2_EnableReadPosition:1;
		Uint32	Enc2_AccessEeprom:1;
		Uint32  Enc2_ResetErrors:1;
		Uint32	Enc2_ResetSTPosition:1;
		Uint32	Enc2_ResetMTPosition:1;
		Uint32  Enc3_EnableReadPosition:1;
		Uint32	Enc3_AccessEeprom:1;
		Uint32  Enc3_ResetErrors:1;
		Uint32	Enc3_ResetSTPosition:1;
		Uint32	Enc3_ResetMTPosition:1;
		Uint32  Enc4_EnableReadPosition:1;
		Uint32	Enc4_AccessEeprom:1;
		Uint32  Enc4_ResetErrors:1;
		Uint32	Enc4_ResetSTPosition:1;
		Uint32	Enc4_ResetMTPosition:1;
		Uint32  Enc5_EnableReadPosition:1;
		Uint32	Enc5_AccessEeprom:1;
		Uint32  Enc5_ResetErrors:1;
		Uint32	Enc5_ResetSTPosition:1;
		Uint32	Enc5_ResetMTPosition:1;
		Uint32  Enc6_EnableReadPosition:1;
		Uint32	Enc6_AccessEeprom:1;
		Uint32  Enc6_ResetErrors:1;
		Uint32	Enc6_ResetSTPosition:1;
		Uint32	Enc6_ResetMTPosition:1;
		Uint32	Reserved:2;
	} bit;
};

union FPGA_STATUS_REG
{
	Uint32	all;
	struct
	{
		Uint32	Enc1_ReadingPosition:1;
		Uint32	Enc1_AccessingEeprom:1;
		Uint32	Enc1_ResettingErrors:1;
		Uint32	Enc1_ResettingSTPosition:1;
		Uint32	Enc1_ResettingMTPosition:1;
		Uint32	Enc2_ReadingPosition:1;
		Uint32	Enc2_AccessingEeprom:1;
		Uint32	Enc2_ResettingErrors:1;
		Uint32	Enc2_ResettingSTPosition:1;
		Uint32	Enc2_ResettingMTPosition:1;
		Uint32	Enc3_ReadingPosition:1;
		Uint32	Enc3_AccessingEeprom:1;
		Uint32	Enc3_ResettingErrors:1;
		Uint32	Enc3_ResettingSTPosition:1;
		Uint32	Enc3_ResettingMTPosition:1;
		Uint32	Enc4_ReadingPosition:1;
		Uint32	Enc4_AccessingEeprom:1;
		Uint32	Enc4_ResettingErrors:1;
		Uint32	Enc4_ResettingSTPosition:1;
		Uint32	Enc4_ResettingMTPosition:1;
		Uint32	Enc5_ReadingPosition:1;
		Uint32	Enc5_AccessingEeprom:1;
		Uint32	Enc5_ResettingErrors:1;
		Uint32	Enc5_ResettingSTPosition:1;
		Uint32	Enc5_ResettingMTPosition:1;
		Uint32	Enc6_ReadingPosition:1;
		Uint32	Enc6_AccessingEeprom:1;
		Uint32	Enc6_ResettingErrors:1;
		Uint32	Enc6_ResettingSTPosition:1;
		Uint32	Enc6_ResettingMTPosition:1;
		Uint32	Reserved:2;
	} bit;
};

union FPGA_INPUT_IO_REG
{
	Uint32 all;
	struct
	{
		Uint32	Input:8;
		Uint32	Reserved:24;
	} bit;
};

union FPGA_OUTPUT_IO_REG
{
	Uint32 all;
	struct
	{
		Uint32 	Output:20;
		Uint32	Reserved:12;
	} bit;
};

union FPGA_PWM_PERIOD_REG
{
	Uint32	all;
	struct
	{
		Uint32	Period:13;
		Uint32	Reserved:19;
	} bit;
};

union FPGA_PWM_DUTY_REG
{
	Uint32	all;
	struct
	{
		Uint32	Duty_HS:13;
		Uint32	Reserved_1:3;
		Uint32	Duty_LS:13;
		Uint32	Reserved_2:3;
	} bit;
};

union FPGA_ENCODER_POSITION_REG
{
	Uint32	all;
	struct
	{
		Uint32	SingleTurn:17;
		Uint32	MultiTurn:15;
	} bit;
};

union FPGA_ENCODER_ERROR_REG
{
	Uint32	all;
	struct
	{
		Uint32	ALMC_BA:1;
		Uint32	ALMC_BE:1;
		Uint32	ALMC_ME:1;
		Uint32	ALMC_OH:1;
		Uint32	ALMC_OF:1;
		Uint32	ALMC_CE:1;
		Uint32	ALMC_FS:1;
		Uint32	ALMC_OS:1;
		Uint32	SF_EA0:1;
		Uint32	SF_EA1:1;
		Uint32	SF_CA0:1;
		Uint32	SF_CA1:1;
		Uint32	COMM_Timeout:1;
		Uint32	COMM_CmdMismatch:1;
		Uint32	COMM_EncIDMismatch:1;
		Uint32	COMM_ChecksumError:1;
		Uint32	Reserved:16;
	} bit;
};

union FPGA_EEPROM_IN_REG
{
	Uint32	all;
	struct
	{
		Uint32	DataIn:8;
		Uint32	Address:7;
		Uint32	AccessType:1;
		Uint32	Reserved:16;
	} bit;
};

union FPGA_EEPROM_OUT_REG
{
	Uint32	all;
	struct
	{
		Uint32	DataOut:8;
		Uint32	ERR_Timeout:1;
		Uint32	ERR_CmdMismatch:1;
		Uint32	ERR_CRC:1;
		Uint32	ERR_AddrMismatch:1;
		Uint32	ERR_WriteBusy:1;
	} bit;
};


struct FPGA_REG
{
	/* SECTION 1: CONTROL, STATUS & ISOLATED I/O REGISTERS */
	union FPGA_CONTROL_REG				ControlReg;
	union FPGA_STATUS_REG				StatusReg;
	Uint32								Reserved_1[6];
	union FPGA_INPUT_IO_REG				IsoInputReg;
	union FPGA_OUTPUT_IO_REG			IsoOutputReg;
	Uint32								Reserved_2[6];

	/* SECTION 2: MOTOR 1 PWM, ENCODER & EEPROM REGISTERS */
	union FPGA_PWM_PERIOD_REG			M1_PwmPeriodReg;
	union FPGA_PWM_DUTY_REG				M1_PwmU_DutyReg;
	union FPGA_PWM_DUTY_REG				M1_PwmV_DutyReg;
	union FPGA_PWM_DUTY_REG				M1_PwmW_DutyReg;
	Uint32								M1_Reserved_1[4];
	union FPGA_ENCODER_POSITION_REG		M1_EncPositionReg;
	union FPGA_ENCODER_ERROR_REG		M1_EncErrorReg;
	union FPGA_EEPROM_IN_REG			M1_EepromInReg;
	union FPGA_EEPROM_OUT_REG			M1_EepromOutReg;
	Uint32								M1_Reserved_2[4];

	/* SECTION 3: MOTOR 2 PWM, ENCODER & EEPROM REGISTERS */
	union FPGA_PWM_PERIOD_REG			M2_PwmPeriodReg;
	union FPGA_PWM_DUTY_REG				M2_PwmU_DutyReg;
	union FPGA_PWM_DUTY_REG				M2_PwmV_DutyReg;
	union FPGA_PWM_DUTY_REG				M2_PwmW_DutyReg;
	Uint32								M2_Reserved_1[4];
	union FPGA_ENCODER_POSITION_REG		M2_EncPositionReg;
	union FPGA_ENCODER_ERROR_REG		M2_EncErrorReg;
	union FPGA_EEPROM_IN_REG			M2_EepromInReg;
	union FPGA_EEPROM_OUT_REG			M2_EepromOutReg;
	Uint32								M2_Reserved_2[4];

	/* SECTION 4: MOTOR 3 PWM, ENCODER & EEPROM REGISTERS */
	union FPGA_PWM_PERIOD_REG			M3_PwmPeriodReg;
	union FPGA_PWM_DUTY_REG				M3_PwmU_DutyReg;
	union FPGA_PWM_DUTY_REG				M3_PwmV_DutyReg;
	union FPGA_PWM_DUTY_REG				M3_PwmW_DutyReg;
	Uint32								M3_Reserved_1[4];
	union FPGA_ENCODER_POSITION_REG		M3_EncPositionReg;
	union FPGA_ENCODER_ERROR_REG		M3_EncErrorReg;
	union FPGA_EEPROM_IN_REG			M3_EepromInReg;
	union FPGA_EEPROM_OUT_REG			M3_EepromOutReg;
	Uint32								M3_Reserved_2[4];

	/* SECTION 5: MOTOR 4 PWM, ENCODER & EEPROM REGISTERS */
	union FPGA_PWM_PERIOD_REG			M4_PwmPeriodReg;
	union FPGA_PWM_DUTY_REG				M4_PwmU_DutyReg;
	union FPGA_PWM_DUTY_REG				M4_PwmV_DutyReg;
	union FPGA_PWM_DUTY_REG				M4_PwmW_DutyReg;
	Uint32								M4_Reserved_1[4];
	union FPGA_ENCODER_POSITION_REG		M4_EncPositionReg;
	union FPGA_ENCODER_ERROR_REG		M4_EncErrorReg;
	union FPGA_EEPROM_IN_REG			M4_EepromInReg;
	union FPGA_EEPROM_OUT_REG			M4_EepromOutReg;
	Uint32								M4_Reserved_2[4];

	/* SECTION 6: MOTOR 5 PWM, ENCODER & EEPROM REGISTERS */
	union FPGA_PWM_PERIOD_REG			M5_PwmPeriodReg;
	union FPGA_PWM_DUTY_REG				M5_PwmU_DutyReg;
	union FPGA_PWM_DUTY_REG				M5_PwmV_DutyReg;
	union FPGA_PWM_DUTY_REG				M5_PwmW_DutyReg;
	Uint32								M5_Reserved_1[4];
	union FPGA_ENCODER_POSITION_REG		M5_EncPositionReg;
	union FPGA_ENCODER_ERROR_REG		M5_EncErrorReg;
	union FPGA_EEPROM_IN_REG			M5_EepromInReg;
	union FPGA_EEPROM_OUT_REG			M5_EepromOutReg;
	Uint32								M5_Reserved_2[4];	

	/* SECTION 7: MOTOR 6 PWM, ENCODER & EEPROM REGISTERS */
	union FPGA_PWM_PERIOD_REG			M6_PwmPeriodReg;
	union FPGA_PWM_DUTY_REG				M6_PwmU_DutyReg;
	union FPGA_PWM_DUTY_REG				M6_PwmV_DutyReg;
	union FPGA_PWM_DUTY_REG				M6_PwmW_DutyReg;
	Uint32								M6_Reserved_1[4];
	union FPGA_ENCODER_POSITION_REG		M6_EncPositionReg;
	union FPGA_ENCODER_ERROR_REG		M6_EncErrorReg;
	union FPGA_EEPROM_IN_REG			M6_EepromInReg;
	union FPGA_EEPROM_OUT_REG			M6_EepromOutReg;
	Uint32								M6_Reserved_2[4];

	/* SECTION 8: UNALLOCATED SPACE */
	Uint32								UNALLOCATED[16];
};


/*** FUNCTION DECLARTION *******************************************************/
void FPGA_SoftReset_InitPin(void);
void FPGA_SoftReset(Uint16 Status);
void Init_Emif1 (void);


/*** EXTERNAL VARIABLE DECLARTION **********************************************/
//extern volatile struct FPGA_REG	FpgaRegs;
extern volatile Uint32 FPGARegs[128];

#endif /* _FPGA_H_ */



